1. Field of the Invention
The present invention relates to a memory testing apparatus suitable to test a semiconductor memory such as a memory in the form of an integrated circuit (an integrated circuit memory, hereinafter referred to as IC memory), and more particularly, to a failure analysis memory for storing test results of a semiconductor memory.
Description of the Related Arts
FIG. 10 shows a basic construction of a conventional memory testing apparatus of this type. The illustrated memory testing apparatus comprises a timing generator TG, a pattern generator PG, a waveform shaping device FC, a logical comparator DC, and a failure analysis memory FM.
The pattern generator PG generates, in response to a reference clock generated by the timing generator TG and supplied thereto, an address signal, a data signal and a control signal which are to be applied to an IC memory under test (hereinafter referred to simply as memory under test) MUT. These signals are supplied to the waveform shaping device FC where they are shaped to have waveforms required for the test, and thereafter they are applied to the memory under test MUT. A data signal written into the memory under test MUT is read out therefrom later and is supplied to the logical comparator DC where the read-out signal is compared with an expected value data signal supplied from the pattern generator PG to detect whether there is an anti-coincidence or a mismatch between both signals or not. If there is a mismatch therebetween, the memory under test MUT is determined to be a failure memory and if there is not, the memory is determined to be a conformable (good or pass) memory.
When there is a mismatch between both signals, a failure signal (failure data) is outputted from the logical comparator DC to the failure analysis memory FM. This failure data is stored in an address of the failure analysis memory FM specified by an address signal from the pattern generator PG. Normally, when there is not a mismatch therebetween, the logical comparator DC generates a pass signal which is not stored in the failure analysis memory FM.
In such a way, information of the failure addresses of the memory under test MUT associated with the failure memory cells which occurred during a series of tests is stored in the failure analysis memory FM. After all of the tests for the memory under test MUT have been completed, a failure analysis of the memory under test MUT is performed with reference to the failure data stored in the failure analysis memory FM. For example, in case such failure data is utilized for relieving failure memory cells of an MUT, a failure map is created based on the read-out failure data from the failure analysis memory FM to determine whether it is possible or not to relieve the detected failure memory cells by relieving means provided on the memory under test MUT.
The failure analysis memory FM has the same operating speed or rate and storage capacity as those of a memory under test MUT, and the same address signal as that applied to the memory under test MUT is applied to the failure analysis memory FM. In addition, the failure analysis memory FM is initialized before a test starts. For example, the failure analysis memory FM is initialized by writing logical "0" in all of the addresses thereof, and when a failure data is generated from the logical comparator DC during a test of the memory under test MUT, logical "1" is written in an address of the failure analysis memory FM specified by the above address signal.
Conventionally, a high speed static type RAM (SRAM) has been used in a failure analysis memory FM. However, an SRAM is expensive and moreover, there is a tendency in recent years that makers each manufacturing high speed SRAMs have no plan for expanding the storage capacity of an SRAM. Consequently, it is difficult to use a high speed SRAM having large storage capacity in a failure analysis memory in correspondence with increase of storage capacity of a memory under test MUT. Therefore, an attempt to use a dynamic type RAM (DRAM) instead of an SRAM to construct a failure analysis memory has been made. A DRAM is inexpensive, but operates at low speed or rate and needs to periodically undergo a refresh operation (an operation for maintaining the stored contents in the DRAM). Since the operation speed (or rate) of a DRAM is slower than that of an SRAM, the number of interleaving a failure analysis memory (the number of parallel processing) must be increased if the failure analysis memory is designed in which its SRAM is simply replaced by a DRAM.
Here, an interleave operation of a memory will be briefly explained. The interleave operation of a memory is a system in which a plurality of memory blocks each having the same storage capacity are provided and those memory blocks are operated at different timings each shifted by a small amount of time interval from the former, thereby increasing the operating speed (or rate) of the memory as a whole. The number of memory blocks is called the number of interleaves and single memory block is also called a bank of interleave. FIG. 11 shows an example of a circuit construction of a failure analysis memory contemplated in case a DRAM is used therein.
As illustrated, a switching circuit MP and a plurality (N) of memory blocks (banks) BK#1, BK#2, BK#3, . . . , BK#N are provided in a failure analysis memory FM (where N is integer equal to or greater than two), and the circuit construction is arranged such that each time a failure data is generated, the switching circuit MP switches the memory blocks BK#1-BK#N in regular sequence to supply the failure data to the corresponding one memory block so that the failure data can be sequentially distributed to and stored in the plurality of memory blocks BK#1, BK#2, BK#3, . . . , BK#N.
As can be easily understood from FIG. 12, by employing this interleave structure, each of the memory blocks BK#1-BK#N suffices to operate at a speed (or rate) of 1/N of the operating speed (or rate) of a memory under test MUT. For example, if there are provided four memory blocks (banks) each operating at a cycle of 100 ns (nanoseconds) and those four memory blocks are operated at different timings shifted by 25 ns from the former, the four memory blocks are deemed as a whole to be equivalent to a memory operating at a cycle of 25 ns.
As a consequence of using a DRAM operating at low speed (or rate) and operating the DRAM in the interleave manner, writing of high speed data in the DRAM and reading of the high speed data therefrom is made possible. However, in case the interleave structure shown in FIG. 11 is employed, an address signal at which a failure signal is generated and the failure signal are randomly supplied to each of the memory blocks BK#1-BK#N, and hence each of the memory blocks BK#1-BK#N must have the same memory capacity as that of a memory under test MUT. As a result, when an interleave structure of N blocks (banks) is arranged, a memory capacity having N times as large as that of a memory under test MUT is required and the amount of usage of memory elements is increased in proportion to the number N of interleaves (memory blocks).
Further, there is a test reffered to an interference test between memory cells among memory testing methods. This interference test between memory cells (hereinafter referred to as inter-cell interference test) is a memory testing method wherein a specific memory cell in a memory under test is noted or interested and when memory cells which are considered to interfere in structure with the interested memory cell (hereinafter referred to as memory cell of interest) are accessed, a test is done to check whether the data of the memory cell of interest is broken by such access of each of those memory cells, this test being done by changing in order the memory cell of interest to another one.
FIGS. 13-15 show three examples of a test pattern used in this inter-cell interference test. FIG. 13 shows a test pattern called a galloping pattern, FIG. 14 shows a test pattern called a ping-pong pattern, and FIG. 15 shows a test pattern called a butterfly pattern. In the butterfly pattern shown in FIG. 15, a reference character Tc denotes a memory cell of interest, reference characters A-D denote interfering memory cells respectively, and reference characters 1-8 denote the sequence of accesses.
As shown in FIGS. 13 to 15, in the inter-cell interference test, the same address of the memory cell of interest is accessed many times in close test cycles. In case the memory cell of interest is a failure memory cell, a failure data is generated in every access to the memory cell of interest, and hence the frequency (the number of times) of writing failure data in the failure analysis memory is increased. In order to perform the writing operation of the failure data in the failure analysis memory in accordance with the writing frequency, the number of interleaving the failure analysis memory must be increased. If the number of interleaving is increased, the amount of memory used must be increased, which results in drawbacks that the cost of the failure analysis memory is increased even if inexpensive DRAMs are used and that the physical size of thereof becomes large.